VHDL laboratory. FPGA design. Using VHDL.
APMF IIR Filter means the filter based on the all-pass multiplier-free filter. The multiplication to the coefficient is implemented in it as a set of additions of the shifted operand. The number of such additions in proposed filters is less or equal to three. The advantages of such kind of filters are small hardware volume, high sampling frequency, low group delay. These filters are free of exitations as well.
The proposed APMF-filters can be built in any FPGA project due to their rather small hardware volume. The filter has the suppression level, which is higher than 30 db. But this level can be improved by combining two or more such filters.
The filter characteristics are shown in the screen, when selecting the 'Show characteristic' radio button in the main window of the filter generator. The programmed cutoff frequency is estimated as the ratio of the circular frequency. I.e. the fraction 0.25 means the sampling frequency multiplied by 0.25. This frequency is given in the range of 0.1 - 0.4.
One of three kinds of the filter can be selected. They are low pass filter (lpf), high pass filter (hpf), and half band filter (hbf). In the last filter the cutoff frequency is equal to 0.25, and one of 27 variants of the filter can be selected inputting an integer. Moreover, such a filter can have two outputs, checking 'Two outputs' mark. These outputs are the output DO of the low pass filter, and the output DOH of the reciprocal high pass filter. Such a filter is suitable for down conversion, multirate filtering, design of filter banks.
The input and output data bit widths can be any integers. But really, the output bit width could not be higher than the input bit width plus three.
The 'Clock enable' check button can add the CE input which can control the clock signal. This is helpful to implement the multirate DSP systems, or to slow-down the filter operation.
The signal at the input RST synchronously resets all the registers of the filter. But in the Xilinx devices when the input RST is not checked, and the reset mode is not implemented, respectively, then the hardware volume is much less due to the fact that the register chains are implemented in the SRL16 primitives. The zero initial state of these registers are set by the GSR signal after configuration.
In the right part of the frame the magnitude frequency diagram of the selected filter is shown. The approximated characteristics of the filter like stop band frequency, stop band ripple, number of adders in it, maximum clock frequency for configuring in Spartan-6 FPGA for 16-bit data are shown below the diagram.
The resulting filter IP core can be freely configured in FPGA of most of companies and most of types. But the inner filter structure is optimized for 6-input logic cells of modern Xilinx, or Altera FPGAs. In the following table the average filter parameters of lpf and hpf filters are shown for some Xilinx FPGAs. These figures are derived for the 16 bit width input and output data and without special synthesis and P&R constraints. They can differ for different cutoff frequencies. Note that Spartan-6 FPGA has 6-input LUTs.
|Hardware volume, CLB slices||77 - 268||77 - 268||77 - 268||76 - 232||76 - 230||76 - 296|
|Clock frequency, MHz||240 - 400||250 - 440||360 - 600||300 - 550||570 - 1000||280 - 440|
When selecting the radio button 'IP core to screen' the VHDL code of the selected filter is outputted to the frame. This text can be moved to the user environment by the Select, Copy, and Paste instructions.
The resulting filter model can be effectively tested using the testbench, which is placed here: Testbench