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SQRT Module is intended for calculating the square root function for the integer argument.

The input and output data bit widths can be any integers which are higher than four.

When the 'Clock input' check button is not selected then the SQRT Module is the bare logic circuit. When it is selected then a set of pipeline registers are set in this circuit.

When selecting the radio button 'Registers at input and output' then two registers are set at the input and the output of the module. When selecting the radio button 'Each 2 stages registered' the additional pipeline registers are set in between each two stages of the multistaged structure of the module. In the case of selecting the button 'Each stage registered' the maximum number of pipeline registers is set in the module. It is obvious that the pipeline registers provide the increase of the maximum clock frequency of the module at the cost of the latent delay increase.

The 'Clock enable' check button can add the CE input which can control the clock signal. This is helpful to slow-down the module operation.

The structure of the SQRT module is distinguished in that, that up to five first iterations of the algorithm are implemented using the look-up tables (LUTs). This helps to minimize the latent delay of the module as well as to decrease the hardware volume. The input bit width of these LUTs is selected in the frame 'LUT address width'. The maximum bit width is equal to ten. Note, that modern Xilinx, and Altera FPGAs are based on 6-bit LUTs.

The resulting IP core can be freely configured in FPGA of most of companies and most of types. In the following table the average parameters of the SQRT module are shown for some Xilinx FPGAs. These figures are derived for the 16 bit width input and output data and without special synthesis and P&R constraints.

When selecting the radio button 'Show characteristics' the approximated characteristics of the SQRT Module for selected input parameters are shown in the right side of the frame. They are hardware volume as the amount of 6-input LUTs, latent delay in clock cycles, and maximum clock frequency for the Xilinx Spartan-6 device. These characteristics are given only for the reference. More precise characteristics can be derived only after configuring this module in the concrete FPGA device.
Note, that when 10-input LUT is eslected, and the synthesis is directed to BlockRAM utilization then the real hardware volume is much less than one which is estimated.

Parameter Pipelining Virtex-4 Spartan-6 Virtex-7
Hardware volume, LUTs No pipelining 281 277309
Hardware volume, LUTs Half pipelined 269 214238
Hardware volume, LUTs Fully pipelined292 275302
Clock frequency, MHz No pipelining 35 3262
Clock frequency, MHz Half pipelined 196 174333
Clock frequency, MHzFully pipelined 298 271552

When selecting the radio button 'IP core to screen' the VHDL code of the selected filter is outputted to the frame. This text can be moved to the user environment by the Select, Copy, and Paste instructions.