VHDL and FPGA design - VHDLлаборатория
VHDL laboratory. FPGA design. Using VHDL.
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Input bit width
DI
SQRT Module
DO
Output bit width
Clock input
CLK
Clock enable
EC
LUT address width
Registers at input and output
Each 2 stages registered
Each stage registered
Show characteristics
IP core to screen
Аdmin.: Tatyana Lesyk
E-mail: lesyk@comsys.ntu-kpi.kiev.ua
Kanyevski's VHDLlaboratory. 2013
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