Minimized FIR Filter Design Implemented in FPGA.

Ju.N. Vinogradov, A. Sergiyenko, S.H. Quadir. Minimized FIR Filter Design Implemented in FPGA. //Proceedings. 20-th Int. Conf. System Analysis and Information Technology, SAIT2018, May 21 – 24, 2018, Kyiv. –P.165-166.

Abstract. The development of the parallel finite impulse response filters for the FPGA implementation is considered. A new method consists in substituting the multipliers to the small coefficients to the ROMs which store the multiplied values of these coefficients. At these costs, the filter hardware volume is minimized and its throughput is increased.
Keywords: FIR filter, FPGA, VHDL

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