Month: February 2020

  • Nano-Processor for the Small Tasks

    O. Molchanov, M. Orlova, A. Sergiyenko. Nano-Processor for the Small Tasks // IEEE 39th International Conference on Electronics and Nanotechnology (ELNANO). 2019/4/16. P.674-677. Abstract—The eight-bit stack processor architecture is proposed, which is designed for the FPGA implementation. The microprocessor with this architecture has small hardware costs, reduced software amount, and ability to add up to hundred new user instructions to its instruction set. The microprocessor architecture is adapted for programming the serial port communications and is able to perform the data stream parsing. It is effectively used for the Internet of Things applications.

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  • System of Feature Extraction for Video Pattern Recognition on FPGA

    O. Molchanov, M. Orlova, A. Sergiyenko, P. Serhiienko. System of Feature Extraction for Video Pattern Recognition on FPGA // IEEE 2nd Ukraine Conference on Electrical and Computer Engineering (UKRCON). 2019. P. 1175-1178. Abstract — A system is proposed for image recognition in a video stream, such as inscriptions, road signs. It is able to recognize the patterns in the complex lighting conditions due to processing the high dynamic range (HDR) signals. The image feature extraction is based on the method, which originated from the Retinex method but is adapted to the HDR images. Due to the new method, the bilateral filter is exchanged to the 2D edge-preserving adaptive filter. The filter output gives information for the feature extraction detectors. The experimental HDR video camera with the feature extraction is built around the Lattice HDR-60 board.

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  • VHDL Generation of Optimized IIR Filters

    A. Sergiyenko, A. Serhienko. VHDL Generation of Optimized IIR Filters // IEEE 2nd Ukraine Conference on Electrical and Computer Engineering (UKRCON). 2019. P. 1171-1174. Abstract — In this paper a method is proposed, which consists in integer coefficient searching, forming the filter structure and modeling it. The use of the VHDL language in all steps of the filter design helps to speed-up the design process and to improve the filter optimization. Examples of the multiplier-less IIR filter design show the method effectiveness. Keywords — VHDL, FPGA, IIR filter, allpass filter

    By Published Publications