A. Sergiyenko, A. Serhienko. VHDL Generation of Optimized IIR Filters // IEEE 2nd Ukraine Conference on Electrical and Computer Engineering (UKRCON). 2019. P. 1171-1174.
Abstract — In this paper a method is proposed, which consists in integer coefficient searching, forming the filter structure and modeling it. The use of the VHDL language in all steps of the filter design helps to speed-up the design process and to improve the filter optimization. Examples of the multiplier-less IIR filter design show the method effectiveness.
Keywords — VHDL, FPGA, IIR filter, allpass filter