A. Sergiyenko, A.Serhienko. Digital Filter Design using VHDL // 5-th International Conference “High Performance Computing” HPC-UA 2018 (Ukraine, Kyiv, October 22-23, 2018). P. 123-126.
Abstract. In this paper a method is proposed, which consists in integer searching for the filter coefficients, forming the filter structure and modeling it. The use of the VHDL language in all the steps of the filter design helps to speed-up and improve the filter optimization. Examples of the multiplierless IIR filter design show the method effectiveness.
Keywords: VHDL, FPGA, IIR filter, allpass filter.