Publications (english)

B O O K S

  1. Sergiyenko A. M., Korneychuk V. I. Computer Networks Engineering. -К.: -“Корнейчук”.-2007.-80 p.

A R T I C L E S   A N D    P A P E R S

after 2000

      1. Ju.N. Vinogradov, A. Sergiyenko, S.H. Quadir. Minimized FIR Filter Design Implemented in FPGA. //Proceedings. 20-th Int. Conf. System Analysis and Information Technology, SAIT2018, May 21 – 24, 2018, Kyiv. –P.165-166.
        Abstract. The development of the parallel finite impulse response filters for the FPGA implementation is considered. A new method consists in substituting the multipliers to the small coefficients to the ROMs which store the multiplied values of these coefficients. At these costs, the filter hardware volume is minimized and its throughput is increased.
        – Text PDF
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      2. A. Sergiyenko, M. J. Hasan, P. A. Serhienko. Square root calculations in FPGA. //Proceedings. 20-th Int. Conf. System Analysis and Information Technology, SAIT2018, May 21 – 24, 2018, Kyiv.– P.163-164
        Abstract. An algorithm and a structure of the square root calculator are improved, so this function is calculated in FPGA three times faster with low hardware costs.
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      3. A. Sergiyenko, P. Serhienko, Ju. Zorin. High Dynamic Range Video Camera with Elements of the Pattern Recognition. //IEEE 38th International Conference on Electronics and Nanotechnology (ELNANO), Kyiv, April 2018. 2018. –P.435-438.
        Abstract. The issues of development of the system for the high dynamic range (HDR) image processing are considered. The HDR images are often used in the medical image processing and pattern recognition. The modified Retinex method for the HDR image compression is proposed, in which the bilateral filter is substituted by the adaptive filter. This edge-preserving filter is based on the Harris-Laplace detectors, and on the Gauss filter with the regulated kernel. The detector outputs give the information about the local properties of the image and can help to perform the effective pattern recognition. The experimental HDR video camera is built on the base of the Lattice HDR-60 board.
        Keywords — HDR; FPGA; Retinex; Bilateral Filter; Feature Extraction.
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      4. A. Sergiyenko, M. R. Quasim. Modeling of the wave propagation in the solid bar. //Proceedings. 20-th Int. Conf. System Analysis and Information Technology, SAIT2018, May 21 – 24, 2018, Kyiv. –P.203-204
        Abstract. The ultrasound propagation wave modeling algorithm is proposed, which consists in representing the medium in the form of a system of the wave digital filters and differs in that due to the implementation of the multichannel filters with the programmable delays, resulting the decrease of the simulation error of the sound propagation dispersion.
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      5. A. Sergiyenko, A. Serhienko, A. Simonenko. A Method for Synchronous Dataflow Retiming. //IEEE First Ukraine Conference on Electrical and Computer Engineering (UKRCON). – 2017. – P. 1015-1018.
        Abstract. A method of retiming the spatial synchronous dataflow graph (SDF) is proposed, which is based on the SDF representation in the multidimensional space. The dimensions of this space are spatial coordinate of the processing unit, coordinate of the operator firing and operator type. At the first stage of the datapath synthesis, the operator nodes are placed in the space according to a set of rules providing the minimum hardware volume and minimum clock period. At the second stage of the synthesis this spatial SDF is balanced and optimized providing the minimum register and multiplexor number in the resulting datapath. The resulting spatial SDF is described by VHDL language and is modeled and compiled using CAD tools.
        Keywords—retiming; SDF, scheduling, pipelining, folding, datapath, FPGA, DSP
        – https://ieeexplore.ieee.org/document/8100404/
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      6. Serhienko A. Modules for Pipelined Mixed Radix FFT Processors. //International Journal of Reconfigurable Computing. — 2016. — P. 1-7.
        Abstract.A set of soft IP cores for the Winograd r-point fast Fourier transform (FFT) is considered. The cores are designed by the method of spatial SDF mapping into the hardware, which provides the minimized hardware volume at the cost of slowdown of the algorithm by r times. Their clock frequency is equal to the data sampling frequency. The cores are intended for the high-speed pipelined FFT processors, which are implemented in FPGA.
        – https://www.hindawi.com/journals/ijrc/2016/3561317/
      7. Maslennikowa N., Sergiyenko A. Tunable Infinite Impulse Responce Filters in FPGA. //Zeszyty Naukowe Wydziału Elektroniki i Informatyki. -Poland: Wyd. Uczelniane Politechniki Koszalińskiej. -2016. -No.9. -P. 43-50.
        Abstract.Features of the dynamically tuned IIR filters, which are configured in FPGA, are considered. The filters utilize the frequency masking properties of the all-pass digital filters, which have the delay factors z-k. The mapping of the filter algorithm is implemented using pipelining and retiming techniques, based on the spatial synchronous dataflow graph, which provides the small hardware volume, and high clock frequency. The smooth stopband frequency tuning is provided by the built-in coefficient calculator.
        Słowa kluczowe: IIR   FPGA   allpass filter   structure synthesis 
         – http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.baztech-432ee24e-19ff-4b2e-9461-55cade28b4ce/c/ZNWEiI-nr9-2.pdf
      8. Application Specific Processors for the Autoregressive Signal Analysis. Maslennikow O., Sergiyenko A., Maslennikowa N., Ratushnyak P., Wozniak M.// Parallel Processing and Applied Mathematic. Part II. -Lecture Notes in Computer Science, Springer. -2010, -V.6068. -p. 126-133.
        – http://kanyevsky.kpi.ua/en/2010/10/05/application-spesific-processors-for-the-ar-signal-analysis/
      9. Anatolij Sergiyenko, Oleg Maslennikow, Piotr Ratuszniak, Natalia Maslennikowa and Adam Tomas . Application Specific Processors for the Autoregressive Signal Analysis //Parallel Processing and Applied Mathematics .Lecture Notes in Computer Science, 2010, Volume 6067/2010, 80-86,
        – http://www.springerlink.com/content/88512547hn1p50t3/
      10. Anatolij Sergiyenko, Dmitry Ivanov, Juriy Vinogradov, Tatyana Lesyk. High Speed AR Analysis Based on FPGA//Праці конференції УкрОбраз ‘2010’ “Signal/Image Processing and Pattern Recognition” -Київ: ІК ім.В.М. Глушкова -2010.
        – http://uasoiro.kibermova.com/files/Zbirnyk/2010/6/p_40.pdf
        Abstract. Two structures of the processors for the autoregressive analysis are considered. The first of them implements the Durbin algorithm using the rational fraction calculations. The second of them implements the adaptive lattice filter. The processors give the possibility of the signal analysis with the sampling frequency up to 300 MHz being configured in FPGA. The processors can be effectively used for adaptive filtering and pattern analysis in the ultrasonic installations, radars, software defined radio, etc.
        – Text PDF
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      11. Sergiyenko A., Maslennikow O., Vinogradow Y. Tensor approach to the application specific processor design//CAD Systems in Microelectronics, 2009. CADSM 2009. 10th International Conference – The Experience of Designing and Application of page(s): 146 – 149 Lviv-Polyana
        – http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?tp=&arnumber=4839787
      12. Sergiyenko A.,Maslennikow O.,Lepekha V.,Tomas A.,Wyrzykowski R. Parallel Implementation of Cholesky LLT -Algorithm in FPGA-Based Processor //Lecture Notes in Computer Science. -Berlin: Springer. -2008. -p. 137 -147.
        – http://www.springerlink.com/content/u35877162x198l41/
      13. Sergiyenko A.,Simonenko V.,Lepekha V. Real time autoregressive processors //Abstracts of Int. Conf. CODATA-21 -Kyiv: NTUU”KPI”. -2008. -p.229-230.
      14. Sergiyenko A.,Lesyk T.,Maslennikow O. Mapping DSP Algorithms into FPGA// Proc. of IEEE East-West Design & Test Symp., EWDTS’08. -Lviv, October 9-13, 2008. -Kharkov: KNURE. -2008. -p.343-348.
      15. Sergiyenko А.,Maslennikow О. Implementation of linear algebra algorithms in the FPGA-based rational fraction arithmetic processor // Abstracts of Int. Conf. CODATA-21 -Kyiv: NTUU”KPI”. -2008. -p.224.
      16. Sergiyenko A.,Maslennikow O.,Ratushniak P. Implementation of Linear Algebra Algorithms in FPGA-based Fractional Arithmetic Units. //Proc. 9-th Int. Conf. “The Experience of Designing and Application of CAD Systems in Microelectronics”, CADSM’2007, -20-24 Feb. 2007, Lviv-Polyana, – p.228-234.
      17. Oleg Maslennikow, Volodymyr Lepekha and Anatoli Sergyienko. FPGA Implementation of the Conjugate Gradient Method
        – http://www.springerlink.com/content/y3223k3650553466/
      18. Anatoli Sergyienko and Oleg Maslennikov. Implementation of Givens QR-Decomposition in FPGA Parallel Processing and Applied Mathematics .Lecture Notes in Computer Science, 2006, Volume 2328/2006, 458-465,
        – http://www.springerlink.com/content/74652txb2fwb7uw0/
      19. Oleg Maslennikow, Anatolij Sergiyenko. Methods of Mapping DSP Algorithms into FPGA //International Symposium on Parallel Computing in Electrical Engineering (PARELEC’06).Bialystok, Poland .September 13-September 17.
        – http://www.computer.org/portal/web/csdl/doi/10.1109/PARELEC.2006.51
      20. Sergiyenko A.,Klimenko A. Sparse matrix solving on FPGA.// Международная конференция информационные технологии в управлении энергетическими системами.-18-19 октября 2005 г.-К.: Украина,-стр. 47-48.
      21. Maslennikov O.,Shevtshenko Ju.,Sergiyenko A. Configurable Microprocessor Array for DSP Applications.// Lecture Notes in Computer Science. -Vol.3019. -2004. -P.36-41.
        – http://www.springerlink.com/content/dger7g7y0ax57b1q/
      22. A. Sergiyenko,O. Maslennikov. Implementation of Givens QR Decomposition in FPGA.// Lecture Notes in Computer Science, Springer, -2002, -Vol. 2328, -p. 453-459.
      23. O. Maslennikov,Ju. Shevtshenko (graduated student),A. Sergyienko. Configurable microcontroller array.//Proc. of the 3-d Int. Conf. on Parallel Computing in Electrical Engineering. PARELEC’2002,-Warsaw, Poland September 22-September 25.-22-25 Sept.,-2002.-P. 47-49.
        – http://www.computer.org/portal/web/csdl/abs/proceedings/parelec/2002/1730/00/17300047abs.htm
      24. Maslennikow O.V.,Wasik A.,Kaniewski J.S.,Maslennikowa N.N. CAD-environment for deriving of application-specific system architectures.// Proc. of the Int.Conf. ICSES’2000 (XXIII KKTOiUE),-Ustron, Poland,-2000,-р.465-470.
      25. Maslennikow O.V.,Wasik A.,Kaniewski J.S.,Maslennikowa N.N. Program environment for designing of application specific FPGA-based parallel architectures.// Proc. of the 7-th Int.Conf. on Mixed Design,MIXDES’2000,-Gdynia,Poland,-2000,-р.191-196.
      26. Guzinski A.,Pawlowski P.,Czwyrow D.,Kaniewski J.,Maslennikow O.,Maslennikowa N., Rataj D. Design of Digital Circuits with Current-Mode Gates.// Bulletin of the Polish Academy of Sciences, Technical Sciences, Vol. 48, No. 1,-2000,-pp.73-91.
      27. Lacinski L.,Wyrzykowski R.,Kaniewski J. Parallel Meshing Algorithm for Finite Element Modeling.// Proc. Int. Workshop Parallel Numerics`2000,-Bratislava (Slovakia), -2000,-pp.117-124.
      28. Maslennikow O.,Wasik A.,Kaniewski J.,Maslennikowa N. Program environment for designing of application specific FPGA-based parallel architectures.// Proc. of the 7-th Int.Conf. on Mixed Design, MIXDES’2000,-Gdynia, Poland,-2000,-pp.191-196.
      29. Gretkowski D.,Maslennikow O.,Kaniewski J. VHDL Models of Digital Sequential Circuits with the Current-Mode Gates.// Proc. of the 7-th Int.Conf. on Mixed Design, MIXDES’2000,-Gdynia,Poland,-2000,-pp.281-286.
      30. Maslennikow O.,Wasik A.,Kaniewski J.,Maslennikowa N. CAD-environment for deriving of application-specific system architectures.// Proc. of the Int.Conf. ICSES’2000 (XXIII KKTOiUE),-Ustron,Poland,-2000,-pp.465-470.
      31. Maslennikow O.,Wasik A.,Gretkowski D.,Kaniewski J. Programowe srodowisko zautomatyzowanego projektowania architektur urzadzen rownoleglych przeznaczonych do implementacji w FPGA i/lub ASIC.// Pracy III Konferencji Krajowej „Reprogramowalne uklady cyfrowe”, RUC’2000,-Szczecin,-2000,-pp.211-218.
      32. Kaniewski J.,Berezowski R.,Gretkowski D.,Maslennikow O.,Soltan P. Modele VHDL filtrow przeznaczonych do realizacji w ukladach FPGA.// Pracy III Konferencji Krajowej „Reprogramowalne uklady cyfrowe”, RUC’2000,-Szczecin,-2000,-pp.269-276.
      33. Gretkowski D.,Lacki M.,Osowicki R. Dydaktyczny model mikroprocesora zrealizowany na ukladach reprogramowalnych.// Pracy III Konferencji Krajowej „Reprogramowalne uklady cyfrowe”, RUC’2000,-Szczecin,-2000,-pp.319-325.

1999

      1. Sergiyenko A.,Kanevski J.,Arefjev A.,Korchev D., A Method for Mapping DSP Algorithms into Pentium MMX Architecture.// Proc. 3-d Int. Conf. On Parallel Processing and Applied Mathematics, PPAM’99,-Kazimierz Dolny, Poland,Sept. 14-17,-1999,-pp.348-356.
      2. Kanevski J.,Maslennikow O.,Maslennikowa N.,Tomas A. Design of FPGA – Based Processor Array Architecture for Linear Algebra Algorithms.//Proc. 3-d Int. Conf. Parallel Processing and Applied Mathematics.-Kazimierz Dolny, Poland, 14-17. Sept. 1999.-Czestohovfa/-1999.-p. 205-216.
      3. Maslennikow O.,Maslennikowa N.,Kaniewski J.,Lacinski L. Analitycal Method for Deriving Dependence Graphs of Recursive Algorithms.// Proc.Int. Workshop Parallel Numerics`99,-Salzburg (Austria),-1999,-pp.41-56.
      4. J.Kaniewski,R.Berezowski,D.Gretkowski,O.Maslennikow and P.Soltan, VHDL-models of parallel FIR digital filters.// Workshop „Signal Processing’99”,-Poznan,Poland,-1999,- pp.95-100.
      5. Gretkowski D.,Berezowski R.,Soltan P. Dydaktyka przedmiotu „Projektowanie ukladow cyfrowych” na Wydziale Elektroniki Politechniki Koszalinskiej.// Pracy II Konferencji Krajowej „Reprogramowalne uklady cyfrowe”, RUC’99,-Szczecin,Poland,-1999,-pp.21-25.
      6. Gretkowski D.,Berezowski R.,Maslennikowa N. Opis i modelowanie cyfrowych ukladow pradowych z wykorzystaniem jezyka VHDL.// Pracy II Konferencji Krajowej „Reprogramowalne uklady cyfrowe”, RUC’99,-Szczecin,Poland,-1999,-pp.165-172.
      7. Maslennikow O.,Kaniewski J.,Gretkowski D. Realizacja algorytmow algebry liniowej na wyspecjalizowanym systemie komputerowym zbudowanym w oparciu o uklady FPGA.// Pracy II Konferencji Krajowej „Reprogramowalne uklady cyfrowe”, RUC’99, -Szczecin,Poland,-1999,-pp.173-181.
      8. Maslennikow O.,Guzinski A.,Kaniewski J.,Berezowski R. Rules of Current-mode Digital Circuit Design and Analysis.// Proc. of the XXII Nat.Conf. on Circuit Theory and Electronic Networks,-Warszawa-Stare Jablonki,Poland,-1999,-pp.149-154.
      9. Gretkowski D.,Kaniewski J.,Maslennikowa N.,Soltan P. Current-mode digital Circuits Design and Modeling.// Proc. of the XXII Nat.Conf. on Circuit Theory and Electronic Networks,-Warszawa-Stare Jablonki,Poland,-1999,-pp.161-167.
      10. Maslennikow O., Maslennikowa N., Guzinski A., Kaniewski J. Approarches to Designing Digital Circuits with the current-mode gates.// Proc. of the 6-th Int.Conf. on Mixed Design, MIXDES’99,-Krakow,Poland,-1999,-pp.89-94.
      11. Gretkowski D.,Guzinski A.,Kaniewski J.,Maslennikow O. VHDL models of digital combinatorical circuits on the current-mode gates.// Proc. 6-th Int.Conf. Mixed design of integrated circuits systems, MIXDES’99,-Krakow,Poland,-1999,-pp.253-258.
      12. Wyrzykowski R.,Szczygio N.,Olace T.,Kaniewski J. Parallel Finite Element Modeling of Solidification Processes.// Lecture Notes in Computer Science, Springer-Verlag, Vol. 1557,-1999,-pp.183-195.
      13. Ju.Kanevski,O.Maslennikov,N.Maslennikova. Design of FPGA-based Processor Array Architecture for Linear Algebra Algorithms Implementation.// Proc. 3-th Int. Conf. Parallel Processing and Applied Mathematics, PPAM’99,-Kazimierz Dolny,Poland,-1999, -p. 205-216.
      14. Gretkowski D.,Kaniewski J.,Maslennikow O.,Wyrzykowski R. A Method for the Design of Bit-Level Parallel Architectures.// Proc.Int. Workshop Parallel Numerics`99, Salzburg (Austria),-1999,-pp.31-40.
      15. Kaniewski J.,Maslennikow O.,Maslennikowa N.,Lacinski L. Analitycal Method for Deriving Dependence Graphs of Recursive Algorithms.// Proc.Int. Workshop Parallel Numerics`99,-Salzburg (Austria),-1999,-pp.41-56.

1998

      1. A.Sergiyenko,J.Kaniewski,O.Maslennikow,R.Wyrzykowski. Mapping Regular Algorithms into Processor Arrays Using Software Pipelining.// Proc.Int. Conf. On Parallel Computing in Electrical Engineering, PARELEC’98,-Bialystoc,Poland,-Sept.2-5,-1998, -pp.197-200.
      2. Kanevski J.,Maslennikov O.,Maslennikova N.,Wyrzykowski R. The modified weighted checksums method for design of the fault tolerant linear algebra algorithms.// Proc. 9-th Europ.Workshop on Dependable Computing,-Gdansk,Poland,-1998,-p.82-85.
      3. Steblyanko V.G.,Marchenko O.I.,Kanevski J. Increasing of special purpouse computer systems software reliability.// Proc. 9-th Europ.Workshop on Dependable Computing,-Gdansk,Poland,-1998,-p.175.
      4. Maslennikov O.,Chvyrov D.,Guzinski A.,Kanevski J.,Pawlowski P. Digital circuits on the current-mode gates.// Proc.Int.Conf. MIXDES’98,-Lodz,Poland,-1998.
      5. Pawlowski P.,Guzinski A.,Kanevski J.,Chvyrov D.,Maslennikov O. Current-mode ternary elements.// Proc.Int.Conf. MIXDES’98,-Lodz,Poland,-1998.
      6. Wyrzykowski R.,Kanevski J.,Maslennikova N.,Maslennikov O. Fault-Tolerant Matrix Decomposition and its Implementation on Processor Arrays.// Engineering Simulation, -England -1998, Vol.15, No.6,-pp.779-814.
      7. Guzinski A.,Pawlowski P.,Kaniewski J.,Czwyrow D.,Maslennikow O. Current-Mode Digital Circuits for Low Voltage Mixed A/D Systems.//Bulletin of the Polish Academy of Sciences, Technical Sciences, Vol. 46, No. 4,-1998,-pp.443-458.
      8. Guzinski A.,Kaniewski J.,Maslennikov O.,Pawlowski P. Current-mode binary and ternary elements.//Proc.Int.Conf. „Computers in Europe. Past, Present and Future”, -Kiev,-1998,-pp.203-212.
      9. Pawlowski P.,Guzinski A.,Kaniewski J.,Maslennikow O.,Czwyrow D. Low-voltage current-mode digital circuits.// Proc. of the XXI Nat.Conf. on Circuit Theory and Elektronic Networks,-Poznan,Poland,-1998,-p.119-124.
      10. Maslennikow O.,Maslennikowa N.,Guzinski A.,Kaniewski J.,Pawlowski P. Design of adders with current-mode gates.// Proc. of the XXI Nat.Conf. on Circuit Theory and Elektronic Networks,-Poznan,Poland,-1998,-p.125-130.
      11. Rataj D.,Kaniewski J.,Guzinski A.,Czwyrow D.,Pawlowski P. Registers and Counters with current-mode gates.// Proc. of the XXI Nat.Conf. on Circuit Theory and Elektronic Networks,-Poznan,Poland,-1998,-pp.131-136.

1997

      1. Maslennikov O.V.,Wyrzykowski R.,Kanevski Ju.S. A New Orthogonal Version of the Gauss-Jordan Algorithm and Its Parallel Implementation.// Proc. Fifth Int. Euromicro Workshop Parallel and Distributed Processing – PDP’97- London, Jan.22-24,-1997,-pp. 445-452.
      2. Kanevski Ju.S.,Sergienko A.M.,Guzinski A. A Method for Mapping Unimodular Loops into Application Specific Parallel Structures.// Proc. of the 2-ndrst Intern. Conf. “Parallel Proc. and Appl., Math. PPAM’97”,-Zakopane,Poland,-1997,-p.362-371.
      3. Wyrzykowski R.,Kanevski Ju.S.,Maslennikov O.V. A New Orthogonal Version of the Gauss-Jordan Algorithm and Its Parallel Implementation.// Proc. Fifth Int. Euromicro Workshop Parallel and Distributed Processing – PDP’97- London, Jan.22-24,-1997,-pp. 445-452.
      4. Maslennikov O.,Chvyrov D.,Guzinski A.,Kanevski J.,Wyrzykowski R. Fault tolerant QR-Decomposition Algorithm Based on Householder Reflections and its Parallel Implementation .// Proc.Int. Workshop Parallel Numerics`97,-Zakopane,Poland, Sept.5-7,-1997,-pp.177-198.
      5. Wyrzykowski R.,Kanevski J.,Maslennikov O.,Gretkowski D. On organization of Control in Processor Arrays.// Proc.Int. Workshop Parallel Numerics`97,-Zakopane,Poland, Sept.5-7,-1997,-pp.199-215.
      6. Wyrzykowski R.,Kanevski J.,Maslennikova N.,Maslennikov O.,Ovramenko S. Formalized Construction Method of Array Functional Graphs for Regular Algorithms.// Engineering Simulation,-1997, Vol.14,-pp.217-232.
      7. Pawlovski P.,Guzinski A.,Kaniewski J.,Czwyrow D. One-bit Adder on Current Gates. //XX Nat.Conf. Circuits Theory and Electronic Networks,-Kolobrzeg,Poland, Oct.21-24,-1997,-pp.115-120.
      8. Czwyrow D.,Guzinski A.,Kaniewski J.,Maslennikow O. Arithmetic-Logic Units on Current Gates.//XX Nat.Conf. Circuits Theory and Electronic Networks,-Kolobrzeg,Poland, Oct.21-24,-1997,-pp.121-126.
      9. Wyrzykowski R.,Kanevski J., A Technique for Mapping Sparse Matrix Computations into Regular Processorr Arrays.// Third Int. Euro-PAR Conf. Parallel Processing, -Passau,Germany, August 1997,-pp.310-317.

1996

      1. Kanevski Ju.S.,Loginova L.M. and Sergienko A.M. Structured Design of Recursive Digital Filters.//Engineering Simulation,-1996, Vol. 13,-pp.381-389.
      2. Lepecha W.,Wyrzykowski R.,Kanevski Ju.S. Mapping sparse matrix computations into processor arrays.// Proc. Int. Workshop Parallel Numerics`96,-Gozd Martuljek,Slovenia, -1996,-pp.86-101.
      3. Kanevski Ju.S.,Loginova L.M. and Sergienko A.M. Structured Design of Recursive Digital Filters.//Engineering Simulation,-1996, Vol. 13,-pp.381-389.
      4. Kanevski Ju.S.,Sergienko A.M.,Maslennikov O.V. Processor Array for Signal Computing and Numerical Applications.// Proc. of the 7-th Int. Conf.”Parcella’96”-Berlin,-1996.-p.47-58.
      5. Kanevski Ju.S.,Wyrzykowski R.,Maslennikov O.V. Algorithm-based fault tolerant solution of linear systems on processor arrays. // Proc.7-th Int Workshop on Parallel Processing by Celluar Automata and Arrays, PARCELLA’96,-Berlin (Germany),-1996, Mathematical Reseach Vol.96,-pp.165-173.
      6. Wyrzykowski R.,Kanevski Ju.S.,Lepecha W. Mapping sparse matrix computations into processor arrays. // Proc. Int. Workshop Parallel Numerics`96,-Gozd Martuljek,Slovenia,-1996,-pp.86-101.
      7. Kanevski Ju.S.,Maslennikowa N.N.,Maslennikov O.V. Algorithm-based fault tolerant solution of linear systems on VLSI processor Arrays. // Proc.Int. Workshop Parallel Numerics`96,-Gozd Martuljek,Slovenia,-1996,-pp.243-244.

1995

      1. Kanevski Ju.S.,Piech H.,Wyrzykowski R. One-dimensional processor arrays for linear algebraic problems.// IEEE Proceedings, Pt. E,-1995, No 1,-pp.1-4.
      2. Kanevski Ju.S.,Maslennikov O.V.,Wyrzykowski R. A method for deriving dependence graphs of recursive algoritms for processor array design.// Int. Workschop “Parallel Numerics’95”,-Sorrento,Italy,-1995 . Napoly,1995.-pp.263-280.
      3. Kanevski Ju.S.,Maslennikova N.N.,Maslennikov O.V.,Wyrzykowski R. Algorithms-based fault tolerant matrix operations on VLSI processor arrays.// Int. Workshop “Parallel Numerics’95”,-Sorrento,Italy,-1995 . Napoly,1995.-pp.281-295.
      4. Kanevski Ju.S.,Wyrzykowski R.,Piech H. One-dimensional processor arrays for linear algebraic problems.// IEE Proc. E, Digit. Comput. Techn.,-1995, N 1,-pp.1-3.
      5. Kanevski Ju.S.,Wyrzykowski R.,Maslennikov O.V. VLSI Implementation of Linear Algebraic Operations based on the Orthogonal Faddeev.//Books of Thes. of the Int. Conf. “ParCo’95”.- Gent,Belgium,Sept.-1995,-p.101.
      6. Kanevski Ju.S.,Wyrzykowski R.,Maslennikov O.V. A method for Deriving Depedence Graphs of Recursive Algorithms for Processor Array Design.// Proc.of the Intern. Workschop “Parallel Numerics’95”.-Sorrento,Italy,Sept.-1995,-p.263-280.
      7. Kanevski Ju.S.,Wyrzykowski R.,Maslennikov O.V.,Maslennikova N.N. Algorithm-Based Fault Tolerant Matrix Traingularization on VLSI Processor Arrays.// Proc. of the Intern. Workschop “Parallel Numerics’95”.-Sorrento,Italy,Sept.-1995,-p.281-295.
      8. Kanevski Ju.S.,Sergienko A.M.,Maslennikov O.V. Processor Array for Signal Computing and Numerical Ap plications.// Proc. of the Int. Conf. “ICSPAT’95”,-Boston,-1995.-p.1563-1567.
      9. Kanevski Ju.S.,Wyrzykowski R.,Piech H. One-dimensional processor arrays for linear algebraic problems.// IEE Proc. E, Comput. Digit. Tech.,-1995,38(1),-pp.1-4.
      10. Kanevski Ju.S.,Wyrzykowski R.,Maslennikov O.V. VLSI Implementation of Linear Algebraic Operations based on the Orthogonal Faddeev.// Books of Thes. of the Int. Conf. “ParCo’95”,-Gent,Belgium,Sept.-1995,-p.101.
      11. Kanevski Ju.S.,Wyrzykowski R.,Maslennikov O.V. A method for Deriving Depedence Graphs of Recursive Algorithms for Processor Array Design.// Proc. of the Intern. Workschop “Parallel Numerics’95”,-Sorrento,Italy,Sept.-1995,-p.263-280.
      12. Kanevski Ju.S.,Wyrzykowski R.,Maslennikov O.V.,Maslennikova N.N. Algorithm-Based Fault Tolerant Matrix Traingularization on VLSI Processor Arrays.// Proc. of the Intern. Workschop “Parallel Numerics’95”,-Sorrento,Italy,Sept.-1995,-p.281-295.
      13. Kanevski Ju.S.,Wyrzykowski R.,Maslennikov O.V.,Maslennikova N.N. Algorithm-Based Fault Tolerant Matrix Traingularization on VLSI Processor Arrays.// Proc. of the Int. Conf. “ICSPAT’95”,-Boston,-1995.-p.2247-2251.

1994

      1. Kanevski Ju.S.,Sergienko A.M.,Piech H. A Method for the Structural Synthes is of Pipelined Array Processors.// Proc. of the First Intern. Conf. “Parallel Proc. and Appl. Math. PRAM’94”,-Czestochova,Poland,-1994,-pp.100-109.
      2. Kanevski Ju.S.,Sergienko A.M. Mapping Numerical Algorithms into Multipipelined Processors.// Proc. of the Int. Workshop “Parallel Numerics’94”,-Smolenice,Slowacja,-pp.192-202.
      3. Kanevski Ju.S.,Sergienko A.M. Mapping Numerical Algorithms into Multipipelined Processors.// Proc.of the Int. Workshop “Parallel Numerics’94”,-Smolenice,Slowacja,-p.192-202.
      4. Kanevski Ju.S.,Maslennikov O.V.,Wyrzykowski R. Systolic-type implementation of matrix computations based on the Faddeev algorithm.// Proc. 1st IEEE Int. Conf. on Massively Parallel Computing Systems,-Ischia,Italy,-1994,-pp.26-37.
      5. Kanevski Ju.S.,Maslennikov O.V.,Wyrzykowski R. Mapping recursive algorithms into processor arrays.// Proc. Int. Workshop “Parallel Numerics’94”,-Smolenice (Slowacja), -pp. 169-191.
      6. Kanevski Ju.S.,Wyrzykowski R.,Piech H. On the design of a parallel multiplier for sparse matrices.// Proc. lst Int. Conf. on Parallel Processing and Applied Mathematics,”PPAM’94”,-Czestochowa,Poland,-1994,-pp.294-304.
      7. Kanevski Ju.S.,Wyrzykowski R.,Elfimova L.D. A fast toroidal systolic array for matrix computations.// Proc. 6th Int. Workschop on Parallel Processing by Cellular Automata and Arrays “Parcella’94”,-Berlin,-1994,-pp.267-272.
      8. Kanevski Ju.S.,Wyrzykowski R.,Maslennikov O.V. Systolic-Type Implementation of Matrix Computations Based on the Faddeev Algorithm.// Proc. of the Intern.-Conf.”Massively Parallel Computing System”,-Ischica,Italy,-1994.
      9. Kanevski Ju.S.,Simonenko V.P.,Loutski G. A new Approach in Solwing Problems in a Distributed Computer Environment During Dynamic Scheduling.//Proc. of the First Intern. Conf.”Parallel Proc. and Appl. Math. PRAM’94”,-Czestochova,Poland,-1994,-p.84-91.
      10. Kanevski Ju.S.,Wyrzykowski R.,Elfimova L. A Fast Toroidal Systolic Array for Matrix Operations.// Proc. of the VI. Int. Workshop “Parallel Proc. by Cellular Automata and Arrays (Parcela’94)”,-Potsdam,-1994,-p.237-245.
      11. Kanevski Ju.S.,Wyrzykowski R.,Maslennikov O.V. Mapping Recursive Algorithms into Processor Arrays.//Proc. of the Int. Workshop “Parallel Numerics’94”,-Smolenice,Slowacja,-p.169-191.

1993

      1. Kanevski Ju.S.,Korchev D.V. Processor arrays for two-dimensional discrete Fourier transform.// IEE PROCEEDINGS-E, Vol. 140, N2.-1993.-P.101-104.
      2. Kanevski Ju.S.,Korchew D.V. Mapping discrete Fourier transforms onto VLSI parallel architectures.// IEEE Proceedings, Pt. E, No.3,-1993.
      3. Kanevski Ju.S.,Piech H.,Wyrzykowski R. New algoritms for series of rectangular matrices and their parallel implementation.// J.Appl.Math.& omp.Sci.,-1993, Vol.3, No 4,-pp.777-790.
      4. Kanevski Ju.S.,Maslennikov O.V.,Wyrzykowski R. Solving matrix algebra problems on linear systolic architectures.// Electronics Modelling,-1993, No 4,-pp.26-33.

1992

      1. Kanevski Ju.S.,Ovramenko S.G.,Wyrzykowski R. Dependence graph transformations in the design of processor arrays for matrix multiplications.// Microproces.& icroprogram.,-1992, Vol.35,-pp.539-544.
      2. Kanevski Ju.S.,Wyrzykowski R.,Elfimova L.D. Systolic architectures for the iterative solution of linear systems.// Cybernetics,-1992,No.5,-pp.145-158.
      3. Kaniewski J.,Wyrzykowski R.,Owramenko S.G. Dependence graph transformations in the design of processor arrays for matrix multiplications.// Microprocessing and Microprogramming.,-1992,-V.135,-North-Holland,-p.534-539. Paris, 1992.

1991

      1. Kanevski Ju.S.,Korchew D.V. A systematic approach to the design of processor Arrays.// Proc.of the Intern. Conf.”Parallel Computing Tehnologies”,-Novosibirsk,-1991.-pp.119-128.
      2. Kanevski Ju.S.,Korchew D.V. Mapping the index set of algorithms variables onto systolic structures.// Cybernetics,-1991, No.1,-pp.51-57.

1990

    1. Kanevski Ju.S.,Owramenko S.G. Compiler of systolic structures.// Proc. Latvian Signal Processing International Conference,-Riga,April 24-26,-1990,-p.188-192.
    2. Kanevski Ju.S.,Kоrchev D.V. Systematic design of systolic FFT-processorc.//Proc. Latvian Signal Processing International Conference,-Riga,April 24-26,-1990,-p.193-197.
    3. Kanevski Ju.S.,Kоrchev D.V. Two-dimensional systilic array for Fast Fourier Trans-form. // Proc. First International Conference on Information Technologies for Image Analysis and Pattern Recognition,- Lviv,Oct. 22-28,-1990,-p.172-176.