# Bachelor degree work themes

**Supervisor D-r Sci, Professor Anatoliy Sergiyenko**

1. **OLED display controller**

*Problem:* To design the project of the controller for the organic light emitting diode display (OLED).

*Controller parameters:*

- display resolution is 128×64 pixels;
- display is grey scale display with 4 bits per pixel;
- controller is the IP core for the Xilinx FPGAs;
- input interface is 2-byte width common bus interface;
- both hexadecimal numbers, characters and graphical information must be displayed;
- controller must be proven in the Avnet evaluation board.

2. **Floating point sine, cosine function calculation module**

*Problem: *To design the project of the module for sine, and cosine calculations.

*Its parameters:*

- floating point number format is selectable as a generic constant;
- module is the IP core for the Xilinx FPGAs.

3.**Gaussian random number generator**

Gaussian random number generator produces the random number flow which distribution function is equal to the Gaussian distribution function.

*Problem: *To design the project of the module for the noise signal generation.

*Its parameters:*

- generator is the IP core for the Xilinx FPGAs;
- sampling frequency of the generated signal musn be no less than 10 MHz;
- a PCB network must be designed which contains both FPGA and DAC for analog signal output.

4. **Floating point adder module**

*Problem:* To design the project of the module for floating point addition.

*Module parameters:*

- floating point number format is selectable as a generic constant;
- both addition and subtraction are implemented;
- computations are implemented in parallel manner;
- module is the IP core for the Xilinx FPGAs;

5. **Floating point square root module**

* Problem:* To design the project of the module for square root calculations.

*Its parameters:*

- floating point number format is selectable as a generic constant;
- module structure is selected from a set of alternative structures due to the hardware volume criterium;
- module is the IP core for the Xilinx FPGAs;

6. **MP-3 Huffman decoder**

MP-3 audio decoder is the well-known device. Huffman decoder is the significant part of it which consumes a large part of decoding computations.

**Problem: **To design the project of the hardwired Huffman decoder for the purposes of decoding speedup and energy consumption minimization.

*Decoder parameters:*

- module is the IP core for the Xilinx FPGAs;
- input data stream satisfies the format of the mp3-file.

7. **Configurable stack-based microprocessor.**

* Features:* microprocessor core is implemented in FPGA, and has minimized hardware volume. The scientific publication is considered.

8. **DES cryptographic module**

*Problem: *To design the project of the standard DES cryptographic module.

*Its parameters:*

- module implements the DES coding of 64-bit words in the pipelined mode;
- the clock frequency is no less than 100 MHz;
- module is the IP core for the Xilinx Spartan3A FPGAs;

9.** FFT processor**

*Problem:* To design the project of the fast Fourier transform (FFT) processor module for implementation in the software-defined radio.

* Its parameters:*

- processor must have the regulated transform width;
- the data and coefficient bit widths must be regulated;
- hrocessor is the IP core for the Xilinx FPGAs;
- the clock frequency and data input sampling rate is no less than 100 MHz;
- the sampling rate is no less than 5 MHz.

10. **DCT processor**

*Problem: *To design the project of the 2-dimensional DCT processor module for implementation of the MPEG-4 video coding.

*Its parameters:*

- module must satisfy the MPEG-4 standard;
- module is the IP core for the Xilinx Spartan3A FPGAs;
- both the clock frequency and data input sampling rate is no less than 100 MHz.

11. **Montgomery multiplier**

*Problem:* To design the project of the Montgomery multiplier for the RSA public key cryptographic module.

*Its parameters are:*

- data bit width is 1024;
- the clock frequency is no less than 100 MHz;
- module is the IP core for the Xilinx Spartan3A FPGAs;
- the Montgomery multiplication of 1024 bit data lasts no longer than 13 microseconds.

12. **Media access controller**

*Problem:* To design the Media access controller (MAC) for the local area network (LAN). MAC is intended to implement the logical level of the LAN. It serves for connection of the physical level LAN circuit to the microprocessor which implements the protocol level of the LAN.

* Its parameters are:*

- the physical level LAN circuit is National DP83847;
- the LAN protocols are 10BASE-T and 100BASE-TX;
- module is the IP core for the Xilinx FPGAs;
- the Media Independent Interface controller for DP83847 must be strictly designed.