# Master’s theses

**In speciality 123 Computer Engineering**

*Theme: Method of hardware simulation of the propagation of ultrasonic waves in a solid.*

http://kanyevsky.kpi.ua/wp-content/uploads/2019/01/Master_Wave_ENG.pdf

ABSTRACT

**Relevance of the topic**. The numerical modeling of the physical
phenomenon of the wave propagation is the basis of many studies and
implementations at the fields of acoustics, ultrasound technology, and radio electronics. The hardware implementation of such a simulation allows us to significantly accelerate and improve the efficiency of devices that use the wave propagation processing. The modern wave propagation simulators use typically the graphic processing units that perform parallel floating-point calculations. Their drawbacks are high cost, high power consumption, and low reliability. The use of the field programmable gate arrays (FPGAs) to simulate the wave processes allows us to increase speed, reduce power consumption of tools that use this simulation. Moreover, the real time simulation of the ultrasonic processes allows us to create the means of ultrasound diagnostics with increased quality of measured results.

**The object of the research** is the high-performance processors for modeling the physical phenomena.

**The subject of the research** is the algorithms and structures of application-specific pipelined processors for modeling the propagation of waves in a solid.

**The objective** is the creation of a method for designing the high-performance processors for the simulation of the acoustic phenomena, which is intended for configuring in FPGA.

**The scientific novelty is as follows:**

1. The ultrasound propagation wave modeling algorithm is improved, which consists in representing the medium in the form of a system of the wave digital filters and differs in that due to the implementation of the multichannel filters with the programmable delays, resulting the decrease of the simulation error of the sound propagation dispersion.

2. A method for the hardware simulation of the ultrasonic wave propagation in a solid is developed, which is based on the implementation of the system of the wave digital filters in the FPGA and is characterized by high speed due to the fact that the filters have a pipelined structure and use the features of the FPGA architecture.

**The practical value of the obtained results** is that the simulation system, built on the proposed method, can be the basis of a new generation of the ultrasonic diagnostic devices that are able to localize the heterogeneities more precisely.

The materials of the thesis were used in the research work “Advanced methods and tools of designing the configurable computers on the basis of mapping the spatial synchronous data flow graphs into the structure for FPGA”, No ДР.047U005087, ФІОТ-30Т / 2017, which is held at NTUU “Igor Sikorsky’s KPI”.

**Approbation of the work.** Substantive provisions and results of the work were presented and discussed at the 20-th International conference “System Analysis and Informational Technologies”, SAIT-2018, May, 21 – 24, 2018, Kyiv, and at the International Conference on Security, Fault Tolerance, Intelligence (ICSFTI2018), May 10 – 12, 2018, Kyiv.

**The structure and scope of the work.** Master’s thesis consists of an introduction, four sections and conclusions.

*The introduction* provides a general description of the work carried out to assess the current state of the problem, justified the relevance of research areas, formulate goals and objectives of research shows the scientific novelty of the obtained results and the practical value of the work, it shows the information about the testing results and their implementation.

*The first section* deals with the basic methods of designing the pipelined application-specific processors, algorithms for the numerical modeling of the physical phenomenon of the wave propagation in the rigid body.

*The second section* describes a general method for the hardware simulation of the ultrasonic wave propagation in a solid.

*The third section* describes the experimental results of the wave propagation simulation in the designed processor.

*The conclusions* describe the results of the work.

The work submitted 80 pages, contains a list of references to the used literature.

**Key words:** FPGA, dispersion, ultrasound, synchronous data flow graph, wave digital filter, pipeline.

*Theme: Method of increasing the efficiency of the finite impulse response digital filters*

http://kanyevsky.kpi.ua/wp-content/uploads/2019/01/Master_FIR_ENG.pdf

ABSTRACT

**Relevance of the topic.** Field programmable gate arrays (FPGAs) are widely used for the high-speed digital signal processing (DSP) in particular for processing by the finite impulse response (FIR) filters. The FIR filter implementation in FPGA is based on the widespread use of hardware multiplication blocks. At the same time, the rest of the FPGA programmable resources are used ineffectively. Therefore, in order to increase the efficiency of the use of the FPGA programmable resources and to reduce their energy consumption, it is necessary to introduce more perfect FIR filter structures.

**The object of the research** is designing of high-performance processors for the digital signal processing.

**The subject of the research** is development of the high-performance pipelined FIR filters.

**The objective** is the creation of a method for designing the high-performance FIR filters which are intended for configuring in FPGA.

**The scientific novelty is as follows:**

The method of increasing the efficiency of the FIR digital filters,
which is based on the fact that the constant coefficient multiplication blocks for the small coefficients are replaced by the specialized blocks, due to which the hardware costs decreases, and the throughput of the filters increases.**The practical value of the obtained results** is that the digital filters developed by the new method allows to improve the efficiency of the DSP systems on the basis of FPGA by reducing their cost or increase the speed. The materials of the thesis were used in the research work “Advanced methods and tools of designing the configurable computers on the basis of mapping the spatial synchronous data flow graphs into the structure for FPGA”, No ДР.047U005087, ФІОТ-30Т / 2017, which is held at NTUU “Igor Sikorsky’s KPI”.

**Approbation of the work.** Substantive provisions and results of the work were presented and discussed at the 20-th International conference “System Analysis and Infirmational Technologies”, SAIT-2018, May, 21 – 24, 2018, Kyiv, and at the International Conference on Security, Fault Tolerance, Intelligence (ICSFTI2018), May 10 – 12, 2018, Kyiv.

**The structure and scope of the work.** Master’s thesis consists of an introduction, four sections and conclusions.

*The introduction* provides a general description of the work carried out to assess the current state of the problem, justified the relevance of research areas, formulate goals and objectives of research shows the scientific novelty of the obtained results and the practical value of the work, it provides the information about the testing results.

*The first section* deals with the features of the modern FPGA architecture, algorithms of digital filtration and their known implementation in FPGA. Here, the basic methods of designing the pipelined application-specific processors, algorithms and structures for calculating the FIR filters are considered.

*The second section* describes a method for increasing the efficiency of FIR digital filters implemented in FPGA.

*In the third section*, the efficiency of using the proposed method is investigated and it is compared with the existing methods of the FIR filter design.

*The conclusions* describe the results of the work.

The work submitted 93 sheets, contains a list of references to the used literature.

**Key words:** FPGA, FIR filter, pipeline, synchronous dataflow graph.

*Theme: Method of increasing the efficiency of devices for the calculation of elementary functions*

http://kanyevsky.kpi.ua/wp-content/uploads/2019/01/Master_SQRT_ENG.pdf

ABSTRACT

**Relevance of the topic.** The field programmable gate array (FPGA) is a modern element basis that is effectively utilized for the high performance implementation of application-specific algorithms with the fixed-point numbers. Very often, such algorithms encounter the calculation of elementary functions. But the suppliers of the FPGA CAD tools do not provide the developers with ready-made high-performance intellectual property cores for calculating the elementary functions, and the providers of such modules distribute them at a high price (about a thousand dollars). In addition, there are no modules among them that can calculate several different functions. Consequently, there are shortages in the design of devices for the calculation of elementary functions in FPGA and they need to be improved.

The purpose of the work: the creation of a method for designing the application specific modules for the elementary function calculation.

**The object of the research** is the computational processes in high-performance application-specific processors.

**The subject of the research** is design of pipelined processors for the elementary function calculations.

**The objective** is the creation of a method for designing the high-performance application-specfic processors for the calculation of elementary functions in FPGA.

**The scientific novelty is as follows:**

1. An algorithm and a structure of the square root calculator are improved, so this function is calculated three times faster with low hardware costs.

2. A method for increasing the efficiency of devices for calculating the elementary functions is developed, which is based on the combination of several algorithms for calculating such functions, which makes it possible to build high-performance multifunction devices.

**The practical value of the results** obtained in the work is that the modules for calculating the elementary functions, which are developed by the proposed method, are ready for use in modern projects of high-performance systems on FPGAs, which are used for digital signal processing, machine learning, image recognition, and others like that.

The materials of the thesis were used in the research work “Advanced methods and tools of designing the configurable computers on the basis of mapping the spatial synchronous data flow graphs into the structure for FPGA”, No ДР.047U005087, ФІОТ-30Т / 2017, which is held at NTUU “Igor Sikorsky’s KPI”.

**Approbation of the work.** Substantive provisions and results of the work were presented and discussed at a 20-th International Conference «System Analysis and Information Technology» SAIT 2018 May 21 – 24, 2018, Kyiv, and International Conference on Security, Fault Tolerance, Intelligence

(ICSFTI2018), May 10 – 12, 2018, Kyiv.

**The structure and scope of work.** Master’s thesis consists of an introduction, three sections and conclusions.

*The introduction* gives a general description of the work, assesses the current state of the problem, substantiates the relevance of the research direction, formulates the purpose and objectives of the research, shows the scientific novelty of the obtained results and the practical value of the work, provides information on the approbation of the results and their implementation.

*In the first section*, the features of the architecture of modern FPGA have been investigated, algorithms for calculation of elementary functions and their known realizations in parallel computing systems and FPGAs are analyzed.

*In the second section*, an algorithm and a square root function calculator are improved, and a method for increasing the efficiency of devices to perform the elementary functions is developed.

*In the third section*, the efficiency of using the proposed square root calculation algorithm and the method of increasing the efficiency of devices for performing the elementary functions are investigated.

*The conclusions* show the results of the work.

The work is presented in 68 pages, contains a reference to the list of used literature and addendums.

**Key words:** FPGA, square root, elementary function, pipeline, SDF graph.