Author: tetiana

  • MALICIOUS HARDWARE IN FPGA

    Anatoliy Sergiyenko, Yuriy Vinogradov, Olexiy Molchanov, Chojadurdy Jepbarov. MALICIOUS HARDWARE IN FPGA//International Conference on Security, Fault Tolerance, Intelligence” (ICSFTI2019). Р. 8-14. Abstract. A survey of malicious hardware in FPGA is considered. The methods for malicious hardware searching and preventing its loading into FPGA are highlighted as well. A conclusion is made that FPGA is the most-safe device against malicious hardware loading. A stack processor structure is proposed which can be used for monitoring the malicious hardware.

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  • Reconfigurable Manycore System

    A. Sergiyenko, O. Molchanov, P. Serhienko. Reconfigurable Manycore System // 5-th International Conference "High Performance Computing" HPC-UA 2018 (Ukraine, Kyiv, October 22-23, 2018). P. 127-130. Abstract. An approach for designing the reconfigurable computing systems in FPGA is proposed, which is based on mapping synchronous data flow graphs to a manycore system. The reconfiguration is performed by switching data flows and exchanging the instruction sets of the processor cores. To implement the processor elements of such a system, a 16-bit RISC-processor core is developed, which has small hardware costs and a configurable instruction set.

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  • Digital Filter Design using VHDL

    A. Sergiyenko, A.Serhienko. Digital Filter Design using VHDL // 5-th International Conference "High Performance Computing" HPC-UA 2018 (Ukraine, Kyiv, October 22-23, 2018). P. 123-126. Abstract. In this paper a method is proposed, which consists in integer searching for the filter coefficients, forming the filter structure and modeling it. The use of the VHDL language in all the steps of the filter design helps to speed-up and improve the filter optimization. Examples of the multiplierless IIR filter design show the method effectiveness. Keywords: VHDL, FPGA, IIR filter, allpass filter.

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  • Hardware Co-design of the Microprocessor for the Serial Port Communications

    O. Molchanov, M. Orlova, A. Sergiyenko. Software/Hardware Co-design of the Microprocessor for the Serial Port Communications // Advances in Computer Science for Engineering and Education II, ICCSEEA'2019, –Springer: –2019. V. 938. P.238–246. Abstract. The eight-bit stack processor architecture is proposed, which is designed for the FPGA implementation. The microprocessor with this architecture has small hardware costs, reduced software amount, and ability to add up to hundred new user instructions to its instruction set. The microprocessor architecture is adapted for programming the serial port communications and is able to perform the data stream parsing.

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  • Nano-Processor for the Small Tasks

    O. Molchanov, M. Orlova, A. Sergiyenko. Nano-Processor for the Small Tasks // IEEE 39th International Conference on Electronics and Nanotechnology (ELNANO). 2019/4/16. P.674-677. Abstract—The eight-bit stack processor architecture is proposed, which is designed for the FPGA implementation. The microprocessor with this architecture has small hardware costs, reduced software amount, and ability to add up to hundred new user instructions to its instruction set. The microprocessor architecture is adapted for programming the serial port communications and is able to perform the data stream parsing. It is effectively used for the Internet of Things applications.

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  • System of Feature Extraction for Video Pattern Recognition on FPGA

    O. Molchanov, M. Orlova, A. Sergiyenko, P. Serhiienko. System of Feature Extraction for Video Pattern Recognition on FPGA // IEEE 2nd Ukraine Conference on Electrical and Computer Engineering (UKRCON). 2019. P. 1175-1178. Abstract — A system is proposed for image recognition in a video stream, such as inscriptions, road signs. It is able to recognize the patterns in the complex lighting conditions due to processing the high dynamic range (HDR) signals. The image feature extraction is based on the method, which originated from the Retinex method but is adapted to the HDR images. Due to the new method, the bilateral filter is exchanged to the 2D edge-preserving adaptive filter. The filter output gives information for the feature extraction detectors. The experimental HDR video camera with the feature extraction is built around the Lattice HDR-60 board.

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  • VHDL Generation of Optimized IIR Filters

    A. Sergiyenko, A. Serhienko. VHDL Generation of Optimized IIR Filters // IEEE 2nd Ukraine Conference on Electrical and Computer Engineering (UKRCON). 2019. P. 1171-1174. Abstract — In this paper a method is proposed, which consists in integer coefficient searching, forming the filter structure and modeling it. The use of the VHDL language in all steps of the filter design helps to speed-up the design process and to improve the filter optimization. Examples of the multiplier-less IIR filter design show the method effectiveness. Keywords — VHDL, FPGA, IIR filter, allpass filter

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