Computational Models for Hardware Implemented Parallel Algorithms

Sergiyenko А.М., Lepekha V.L., Lesyk T.M. Computational Models for Hardware Implemented Parallel Algorithms //Proceedings of Yubilee International Scientific-Practical Conf. in 50-th Anniversary of the Computer Science Dep-t. -Kiev, 6-8 April 2010. –Kiev: NTUU «KPI». –p.125-127. (In Russian)

Data flow graph (DFG) is a natural model for data flow algorithm representation. A classification of different DFGs is presented. It is shown that pipelined datapaths are designed on the base of mapping synchronous DFG (SDF) or DFG with effective behavior, and quasi static DFG. Uniform SDF has higher complexity of algorithm representation than multirate SDF has. But uniform SDF represented in the multidimensional space can be mapped into the optimized datapath structure formally, and with minimized hardware volume.

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Computational Models for Hardware Implemented Parallel Algorithms.(russian)

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