Tunable IIR Filters, Implemented in FPGA

Sergiyenko А.М., Lesyk T.M. Tunable IIR Filters, Implemented in FPGA // Bulletin of NTUU «KPI», Informatics, Control and Computer Science. -V.52. -2010. -p.47-51. (in Russian)

Features of the dynamically tuned IIR filters, which are configured in FPGA, are considered. The filters utilize the frequency masking properties of the all-pass digital filters, which have the delay factors z-k. The mapping of the filter algorithm is implemented using pipelining and C-slow retiming techniques, which provide the minimized hardware volume and high clock frequency of the resulting filters.

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Tunable IIR Filters, Implemented in FPGA.(russian)

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